US 12,073,915 B2
Memory device, operation method of memory device, and page buffer included in memory device
Yongsung Cho, Hwaseong-si (KR); Min Hwi Kim, Suwon-si (KR); and Ji-Sang Lee, Iksan-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Aug. 16, 2022, as Appl. No. 17/888,661.
Claims priority of application No. 10-2021-0108966 (KR), filed on Aug. 18, 2021.
Prior Publication US 2023/0060080 A1, Feb. 23, 2023
Int. Cl. G11C 7/20 (2006.01); G11C 7/06 (2006.01); G11C 7/10 (2006.01); G11C 7/12 (2006.01)
CPC G11C 7/20 (2013.01) [G11C 7/065 (2013.01); G11C 7/1039 (2013.01); G11C 7/12 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory cell array including a plurality of memory cells;
a plurality of data latches connected with a sensing node, and configured to store data that is to be stored in a first memory cell of the plurality of memory cells;
a sensing latch connected with the sensing node;
a temporary storage node;
a switch connected between the sensing latch and the temporary storage node, and configured to operate in response to a temporary storage node setup signal;
a first precharge circuit configured to selectively precharge a first bit line corresponding to the first memory cell, the selectively precharging the first bit line depending on a level of the temporary storage node; and
a control logic circuit configured to control a dump operation between the plurality of data latches, the sensing latch, and the temporary storage node,
wherein the control logic circuit is configured to perform the dump operation from the plurality of data latches to the sensing latch while the first precharge circuit selectively precharges the first bit line.