US 12,073,913 B2
Synchronous input buffer control using a state machine
Kallol Mazumder, Dallas, TX (US); and Navya Sri Sreeram, Plano, TX (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 23, 2022, as Appl. No. 17/821,740.
Prior Publication US 2024/0071436 A1, Feb. 29, 2024
Int. Cl. G11C 7/10 (2006.01)
CPC G11C 7/1084 (2013.01) [G11C 7/1069 (2013.01); G11C 7/1093 (2013.01); G11C 7/1096 (2013.01)] 26 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a command interface configured to receive write commands from a host device;
an input buffer configured to buffer data from the host device; and
a state machine configured to:
receive a command into a first partition of the state machine;
enable a data strobe (DQS) input buffer in response to the command being received into the first partition;
maintain the enablement of the DQS input buffer while the command traverses the state machine; and
after a set duration of time, disabling the DQS input buffer.