US 12,073,910 B2
Semiconductor memory devices
Jongcheol Kim, Suwon-si (KR); Hyunsung Shin, Suwon-si (KR); Hohyun Shin, Suwon-si (KR); Taeyoung Oh, Suwon-si (KR); and Kyungsoo Ha, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Feb. 15, 2023, as Appl. No. 18/169,769.
Claims priority of application No. 10-2022-0084779 (KR), filed on Jul. 11, 2022.
Prior Publication US 2024/0012712 A1, Jan. 11, 2024
Int. Cl. G11C 7/10 (2006.01); G06F 3/06 (2006.01); G11C 11/4093 (2006.01); G11C 11/4096 (2006.01); G06F 11/10 (2006.01); G11C 11/408 (2006.01)
CPC G11C 7/1012 (2013.01) [G06F 3/0619 (2013.01); G11C 11/4093 (2013.01); G11C 11/4096 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 11/1068 (2013.01); G11C 11/4082 (2013.01); G11C 2207/005 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a memory cell array including a plurality of sub array blocks arranged in a first direction and in a second direction crossing the first direction, each of the plurality of sub array blocks including a plurality of memory cells;
a data input/output (I/O) buffer configured to exchange data with a memory controller through a plurality of I/O pads;
an I/O gating circuit, connected to the data I/O buffer through a plurality of data buses and connected to the memory cell array through a plurality of data I/O lines, the I/O gating circuit configured to:
receive a mapping control signal, and
based on the mapping control signal, set a mapping relationship between the plurality of sub array blocks in which the data is stored and the plurality of I/O pads through which the data is transferred; and
a control logic circuit configured to generate the mapping control signal based on identifier information about a central processing unit (CPU) of the memory controller.