US 12,073,909 B2
Page buffer circuit and memory device including the same
Yongsung Cho, Hwaseong-si (KR); Jinwoo Park, Hwaseong-si (KR); Hyunjun Yoon, Changwon-si (KR); and Yoonhee Choi, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Dec. 21, 2022, as Appl. No. 18/085,963.
Application 18/085,963 is a continuation of application No. 17/222,024, filed on Apr. 5, 2021, granted, now 11,568,903.
Claims priority of application No. 10-2020-0111281 (KR), filed on Sep. 1, 2020.
Prior Publication US 2023/0131700 A1, Apr. 27, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/06 (2006.01); G11C 7/06 (2006.01); G11C 7/10 (2006.01); G11C 16/34 (2006.01)
CPC G11C 7/065 (2013.01) [G11C 7/1039 (2013.01); G11C 7/1057 (2013.01); G11C 7/1084 (2013.01); G11C 16/3404 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory cell array including a plurality of memory cell groups;
a page buffer circuit including a plurality of page buffer groups respectively connected to the plurality of memory cell groups, wherein:
each of the plurality of page buffer groups comprises a plurality of page buffer units arranged in a matrix form, and
a plurality of first page buffer units in a first stage of each page buffer group are divided into a first group configured to perform a first sensing operation according to a first sensing signal and a second group configured to perform a second sensing operation according to a second sensing signal;
a counting circuit configured to count a first number of memory cells included in a first threshold voltage region from a result of the first sensing operation, and count a second number of memory cells included in a second threshold voltage region from a result of the second sensing operation; and
a control circuit configured to determine a development time period of the plurality of first page buffer units based on a comparison result of the first number of memory cells and the second number of memory cells,
wherein the plurality of page buffer groups comprise a first page buffer group, a second page buffer group, a third page buffer group, and a fourth page buffer group, and
wherein the memory device further comprises:
a first page buffer decoder configured to generate a first current corresponding to a number of memory cells included in the first threshold voltage region from page buffer units of the first group of the first and second page buffer groups, and generate a second current corresponding to a number of memory cells included in the second threshold voltage region from page buffer units of the second group of the first and second page buffer groups; and
a second page buffer decoder configured to generate a third current corresponding to a number of memory cells included in the first threshold voltage region from page buffer units of the first group of the third and fourth page buffer groups, and generate a fourth current corresponding to a number of memory cells included in the second threshold voltage region from page buffer units of the second group of the third and fourth page buffer groups.