US 12,073,907 B2
Interconnections for 3D memory
Toru Tanzawa, Tokyo (JP)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 14, 2022, as Appl. No. 17/693,871.
Application 16/406,277 is a division of application No. 16/137,309, filed on Sep. 20, 2018, granted, now 10,304,498, issued on May 28, 2019.
Application 14/813,711 is a division of application No. 13/774,522, filed on Feb. 22, 2013, granted, now 9,111,591, issued on Aug. 18, 2015.
Application 17/693,871 is a continuation of application No. 16/921,206, filed on Jul. 6, 2020, granted, now 11,276,437.
Application 16/921,206 is a continuation of application No. 16/406,277, filed on May 8, 2019, granted, now 10,706,895, issued on Jul. 7, 2020.
Application 16/137,309 is a continuation of application No. 15/878,121, filed on Jan. 23, 2018, granted, now 10,109,325, issued on Oct. 23, 2018.
Application 15/878,121 is a continuation of application No. 15/692,512, filed on Aug. 31, 2017, granted, now 9,881,651, issued on Jan. 30, 2018.
Application 15/692,512 is a continuation of application No. 15/164,400, filed on May 25, 2016, granted, now 9,786,334, issued on Oct. 10, 2017.
Application 15/164,400 is a continuation of application No. 14/813,711, filed on Jul. 30, 2015, granted, now 9,368,216, issued on Jun. 14, 2016.
Prior Publication US 2022/0277777 A1, Sep. 1, 2022
Int. Cl. G11C 16/06 (2006.01); G11C 5/02 (2006.01); G11C 5/06 (2006.01); G11C 7/12 (2006.01); G11C 7/22 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01); H10B 41/20 (2023.01); H10B 41/35 (2023.01); H10B 41/41 (2023.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/16 (2006.01)
CPC G11C 5/063 (2013.01) [G11C 5/02 (2013.01); G11C 5/06 (2013.01); G11C 7/12 (2013.01); G11C 7/222 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); H10B 41/20 (2023.02); H10B 41/35 (2023.02); H10B 41/41 (2023.02); G11C 16/0483 (2013.01); G11C 16/06 (2013.01); G11C 16/08 (2013.01); G11C 16/16 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A method, comprising:
providing a first voltage to a first control line associated with a memory array;
providing a second voltage to a second control line associated with the memory array;
performing a read operation involving the memory array;
discharging the first control line and the second control line to an equalization potential after performance of the read operation involving the memory array; and
discharging the equalized first control line and the second control line to a ground reference potential.