US 12,073,905 B2
Adaptive error avoidance in the memory devices
Li-Te Chang, San Jose, CA (US); Yu-Chung Lien, San Jose, CA (US); Murong Lang, San Jose, CA (US); Zhenming Zhou, San Jose, CA (US); and Michael G. Miller, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 24, 2022, as Appl. No. 17/894,528.
Prior Publication US 2024/0071553 A1, Feb. 29, 2024
Int. Cl. G11C 29/52 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 16/34 (2006.01)
CPC G11C 29/52 (2013.01) [G11C 16/08 (2013.01); G11C 16/102 (2013.01); G11C 16/3404 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
receiving, by a processing device, a request to perform a memory access operation with respect to a set of memory cells connected to a wordline of a memory device;
identifying a block family associated with the set of memory cells;
determining, for each logical programming level of a plurality of logical programming levels, a corresponding default block family error avoidance (BFEA) threshold voltage offset value associated with the block family;
determining a value of a data state metric associated with the set of memory cells;
responsive to determining that the value of the data state metric satisfies a threshold criterion, determining, for each logical programming level of a plurality of logical programming levels, a corresponding sub-BFEA threshold voltage offset value; and
performing the memory access operation by applying, for each logical programming level of the plurality of logical programming levels, a combination of the default BFEA threshold voltage value, the sub-BFEA threshold voltage value, and a corresponding base voltage level.