US 12,073,898 B2
Nonvolatile memory including on-die-termination circuit and storage device including the nonvolatile memory
Eun-Ji Kim, Suwon-si (KR); Jung-June Park, Seoul (KR); Jeong-Don Ihm, Seongnam-si (KR); Byung-Hoon Jeong, Hwaseong-si (KR); and Young-Don Choi, Seoul (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jul. 28, 2023, as Appl. No. 18/361,132.
Application 18/361,132 is a continuation of application No. 17/704,345, filed on Mar. 25, 2022, granted, now 11,742,040.
Application 17/704,345 is a continuation of application No. 17/161,995, filed on Jan. 29, 2021, granted, now 11,342,038, issued on May 24, 2022.
Application 17/161,995 is a continuation of application No. 16/862,624, filed on Apr. 30, 2020, granted, now 11,024,400, issued on Jun. 1, 2021.
Application 16/862,624 is a continuation of application No. 16/458,933, filed on Jul. 1, 2019, granted, now 10,559,373, issued on Feb. 11, 2020.
Application 16/458,933 is a continuation of application No. 16/426,391, filed on May 30, 2019, granted, now 10,679,717, issued on Jun. 9, 2020.
Application 16/426,391 is a continuation of application No. 15/977,553, filed on May 11, 2018, granted, now 10,340,022, issued on Jul. 2, 2019.
Claims priority of provisional application 62/506,641, filed on May 16, 2017.
Claims priority of application No. 10-2017-0121313 (KR), filed on Sep. 20, 2017.
Prior Publication US 2024/0021259 A1, Jan. 18, 2024
Int. Cl. G11C 5/06 (2006.01); G11C 7/10 (2006.01); G11C 16/06 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01); G11C 29/02 (2006.01)
CPC G11C 29/025 (2013.01) [G11C 5/063 (2013.01); G11C 7/1048 (2013.01); G11C 7/1057 (2013.01); G11C 7/1084 (2013.01); G11C 16/06 (2013.01); G11C 16/102 (2013.01); G11C 16/26 (2013.01); G11C 29/022 (2013.01); G11C 29/028 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A nonvolatile memory (NVM) device comprising:
a first NVM chip and a second NVM chip;
a data pin configured to transmit read data to a controller through a data bus during a read operation, and receive write data from the controller through the data bus during a write operation;
a data strobe pin configured to transmit a data strobe signal to the controller through a data strobe signal bus during the read operation, and receive the data strobe signal from the controller through the data strobe signal bus during the write operation;
a read enable pin configured to receive a read enable signal from the controller through a read enable signal bus; and
an on-die termination (ODT) pin configured to receive an ODT signal from the controller during the read operation, and receive the ODT signal from the controller during the write operation,
wherein the ODT signal enables and disables termination on at least one of the data bus, the data strobe signal bus, and the read enable signal bus,
wherein the read enable signal is a logic low level when the ODT signal transitions to an enable level, during the read operation, and
wherein the read enable signal is a logic high level when the ODT signal transitions to the enable level, during the write operation.