US 12,073,896 B2
Memory system and operating method of the memory system
Gil Bok Choi, Icheon-si (KR); Moon Sik Seo, Icheon-si (KR); and Dae Hwan Yun, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Aug. 18, 2022, as Appl. No. 17/890,784.
Claims priority of application No. 10-2022-0035814 (KR), filed on Mar. 23, 2022.
Prior Publication US 2023/0307073 A1, Sep. 28, 2023
Int. Cl. G11C 16/06 (2006.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 16/16 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/3495 (2013.01) [G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/16 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A memory system, comprising:
a plurality of semiconductor memory devices each of which includes a plurality of memory blocks; and
a controller configured to control the plurality of semiconductor memory devices to perform a program operation, a read operation, and an operation of removing a hole in a space region on a target memory block of the plurality of memory blocks,
wherein the controller controls the plurality of semiconductor memory devices to perform the operation of removing the hole in the space region on the target memory block when an erase count of the target memory block is greater than a set value.