CPC G11C 16/3459 (2013.01) [G11C 16/08 (2013.01); G11C 16/102 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); G11C 16/30 (2013.01); G11C 16/3404 (2013.01)] | 20 Claims |
1. A method of operating a semiconductor memory device programming selected memory cells to store N bits of data in each of the selected memory cells, the method comprising:
foggy programming for increasing threshold voltages of first memory cells to be programmed to (2N−1)th to (2N−1)th target program states, among first to (2N−1)th target program states, to an intermediate program state by using an intermediate verify voltage; and
fine programming for programming the selected memory cells to target program states by using first to (2N−1)th verify voltages,
wherein the fine programming comprises increasing the threshold voltages of the first memory cells to be programmed to the (2N−1)th to (2N−1)th target program states and increasing threshold voltages of second memory cells to be programmed to the first to (2N−1−1)th target program states,
wherein the second memory cells are programmed at a different time from the first memory cells,
wherein N is a natural number greater than 1,
wherein when the fine programming of the first memory cells is suspended, a first read operation to resume the fine programming of the first memory cells is performed using a first read voltage between an erase state and the intermediate verify voltage, and
wherein when the fine programming of the second memory cells is suspended, a second read operation to resume the fine programming of the second memory cells is performed using a second read voltage between the threshold voltages of the first memory cells and the threshold voltages of the second memory cells.
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