CPC G11C 16/3427 (2013.01) [G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/3459 (2013.01)] | 17 Claims |
1. A semiconductor memory device, comprising:
a memory cell array including a plurality of memory blocks coupled to a common source line;
a peripheral circuit configured to perform a program operation on a selected memory block selected from among the plurality of memory blocks included in the memory cell array; and
control logic configured to control the program operation of the peripheral circuit,
wherein the plurality of memory blocks are coupled to corresponding source select lines, respectively,
wherein the program operation comprises a plurality of program loops, each program loop including a channel precharge operation and a program pulse application operation,
wherein the control logic is configured to control, during the channel precharge operation, the peripheral circuit to:
allow the common source line to float, and
increase a voltage of a source select line coupled to an unselected memory block among the plurality of memory blocks while the common source line floats,
wherein the control logic is configured to control the peripheral circuit to perform the program pulse application operation to apply a program voltage to a selected word line among a plurality of word lines included in the selected memory block after performing the channel precharge operation.
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