US 12,073,892 B2
Simplified operations to read memory cells coarsely programmed via interleaved two-pass data programming techniques
Phong Sy Nguyen, Livermore, CA (US); James Fitzpatrick, Laguna Niguel, CA (US); and Kishore Kumar Muchherla, Fremont, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Sep. 8, 2022, as Appl. No. 17/940,317.
Application 17/940,317 is a continuation of application No. 17/127,476, filed on Dec. 18, 2020, granted, now 11,456,038.
Prior Publication US 2023/0005552 A1, Jan. 5, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/34 (2006.01); G11C 7/10 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01); G11C 16/30 (2006.01)
CPC G11C 16/3404 (2013.01) [G11C 7/106 (2013.01); G11C 7/1087 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); G11C 16/30 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device, comprising:
memory cells;
latches; and
a circuit configured to:
receive, in the latches, a first number of groups of data bits;
program, in a first pass, the memory cells to store the first number of groups of data bits;
determine a group identification of a first group among a plurality of threshold level groups;
read a second number of groups of data bits into the latches, based on the group identification for the respective memory cell;
determine the first number of groups of data bits in the latches; and
program, in a second pass, the memory cells to store the first number of groups of data bits loaded into the latches via reading the memory cells.