US 12,073,891 B2
Integrated command to calibrate read voltage level
Eric N. Lee, San Jose, CA (US); Violante Moschiano, Avezzano (IT); Jeffrey S. McNeil, Nampa, ID (US); James Fitzpatrick, Laguna Niguel, CA (US); Sivagnanam Parthasarathy, Carlsbad, CA (US); Kishore Kumar Muchherla, Fremont, CA (US); and Patrick R. Khayat, San Diego, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Feb. 28, 2022, as Appl. No. 17/682,089.
Claims priority of provisional application 63/239,736, filed on Sep. 1, 2021.
Prior Publication US 2023/0062445 A1, Mar. 2, 2023
Int. Cl. G11C 16/30 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01)
CPC G11C 16/30 (2013.01) [G11C 16/102 (2013.01); G11C 16/26 (2013.01); G11C 2207/2254 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory array comprising a set of memory cells; and
processing logic, operatively coupled with the memory array, to perform operations comprising:
receiving, from a memory sub-system controller, a command to execute a set of read operations at a plurality of read voltage levels corresponding to a programming distribution associated with the memory device;
determining, in response to the command, a set of memory bit counts, where each memory bit count corresponds to a respective bin of a set of bins associated with the plurality of read voltage levels of the set of read operations;
identifying, in response to the command, a valley center bin having a minimum memory bit count of the set of memory bit counts;
determining, in response to the command, that the minimum memory bit count of the valley center bin satisfies a condition, wherein the condition is satisfied when the minimum memory bit count of the valley center bin is less than a valley margin threshold; and
identifying, in response to the command, an adjusted read voltage level associated with the valley center bin in response to the condition being satisfied.