CPC G11C 16/26 (2013.01) [G11C 11/5671 (2013.01); G11C 16/0483 (2013.01); H10B 43/27 (2023.02); H10B 43/35 (2023.02)] | 15 Claims |
1. A method of controlling a semiconductor memory device including a plurality of memory cells and a word line coupled to the plurality of memory cells, wherein each of the plurality of memory cells is configured to store n-bit data, and n is an integer of three or more, the method comprising:
controlling the plurality of memory cells to store the n-bit data by correlating the n-bit data with first to 2n-th threshold voltage regions, wherein a voltage of a (k+1)-th threshold voltage region is higher than that of a k-th threshold voltage region, k is an integer greater than or equal to one, and k is an integer smaller than 2n;
performing a first read operation corresponding to first to fourth read levels, in order to optimize first to fourth read voltages corresponding to the first to fourth read levels;
determining the first to fourth read voltages based on a result of the first read operation; and
determining fifth to (2n−1)-th read voltages based on the determined first to fourth read voltages, the fifth to (2n−1)-th read voltages corresponding to fifth to (2n−1)-th read levels, wherein
the first read level is between the first threshold voltage region and the second threshold voltage region,
the second read level is between the (2n−1)-th threshold voltage region and the 2n-th threshold voltage region,
the third read level is between a p-th threshold voltage region and a (p+1)-th threshold voltage region, wherein p is an integer greater than one and smaller than (2n−1), and
the fourth read level is between a q-th threshold voltage region and a (q+1)-th threshold voltage region, wherein q is an integer greater than one and smaller than (2n−1), and q is different from p.
|