US 12,073,886 B2
Semiconductor memory device with write disturb reduction
Christopher J. Petti, Mountain View, CA (US)
Assigned to SUNRISE MEMORY CORPORATION, San Jose, CA (US)
Filed by SUNRISE MEMORY CORPORATION, San Jose, CA (US)
Filed on Mar. 2, 2022, as Appl. No. 17/685,133.
Claims priority of provisional application 63/159,260, filed on Mar. 10, 2021.
Prior Publication US 2022/0293188 A1, Sep. 15, 2022
Int. Cl. G11C 7/00 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 16/24 (2006.01); G11C 16/26 (2006.01)
CPC G11C 16/102 (2013.01) [G11C 16/08 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01)] 24 Claims
OG exemplary drawing
 
1. A method for reducing write disturb in an array of memory cells arranged in a plurality of memory pages, each memory page comprising memory cells arranged in rows and columns, the method comprising:
selecting a row of memory cells in a first memory page for a write operation to store write data into the memory cells;
determining a step order value indicative of a write step order of the write operation;
in response to the step order value having a first logical state, performing the write operation by writing data of a first logical state in all the memory cells in the selected row followed by writing data of a second logical state in at least a subset of memory cells in the selected row in response to the write data; and
in response to the step order value having a second logical state, performing the write operation by writing data of the second logical state in all the memory cells in the selected row followed by writing data of the first logical state in at least a subset of memory cells in the selected row in response to the write data.