US 12,073,876 B2
Memory clock level-shifting buffer with extended range
Harold Pilo, Underhill, VT (US)
Assigned to Synopsys, Inc., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Mountain View, CA (US)
Filed on Aug. 19, 2022, as Appl. No. 17/891,395.
Prior Publication US 2024/0062810 A1, Feb. 22, 2024
Int. Cl. G11C 8/00 (2006.01); G11C 11/418 (2006.01)
CPC G11C 11/418 (2013.01) 20 Claims
OG exemplary drawing
 
1. A level shifter circuit, comprising:
a level shifter configured to receive a first clock signal associated with a first power level (VDDP) and generate a second clock signal associated with a second power level (VDDA), wherein the second power level is greater than the first power level; and
an input clock buffer comprising a first input, wherein the first input comprises the second clock signal from the level shifter, and a second input coupled in parallel to the first input, wherein the second input comprises the first clock signal.