US 12,073,875 B2
Receiver with pipeline structure for receiving multi-level signal and memory device including the same
Hyunsub Rie, Yongin-si (KR); Eunseok Shin, Seoul (KR); Youngdon Choi, Seoul (KR); Changsoo Yoon, Seoul (KR); Hyunyoon Cho, Uiwang-si (KR); and Junghwan Choi, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Sep. 13, 2022, as Appl. No. 17/943,448.
Claims priority of application No. 10-2021-0133154 (KR), filed on Oct. 7, 2021.
Prior Publication US 2023/0116188 A1, Apr. 13, 2023
Int. Cl. G11C 16/34 (2006.01); G11C 11/4096 (2006.01); H03M 1/12 (2006.01)
CPC G11C 11/4096 (2013.01) [H03M 1/124 (2013.01); G11C 16/34 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A receiver configured to receive a multi-level signal having three or more voltage levels that are different from each other, the receiver comprising:
a sample and hold circuit configured to generate a sample data signal by sampling and holding an input data signal that is the multi-level signal;
a first analog-to-digital converting circuit configured to generate a first bit of output data based on the input data signal and a first selection reference voltage among a plurality of reference voltages, the output data including at least the first bit and a second bit;
a digital-to-analog converting circuit configured to select at least one additional selection reference voltage from among the plurality of reference voltages based on the first bit of the output data, the at least one additional selection reference voltage being different from the first selection reference voltage; and
a second analog-to-digital converting circuit configured to generate at least the second bit of the output data based on the sample data signal and the at least one additional selection reference voltage.