| CPC G11C 11/4093 (2013.01) [G11C 11/4087 (2013.01); G11C 11/4091 (2013.01); G11C 11/4097 (2013.01)] | 8 Claims |
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1. An apparatus comprising:
a memory array comprising a first plurality of memory cells in a first physical address space and a second plurality of memory cells in a second physical address space;
a data bus coupled to the first and the second pluralities of memory cells via a plurality of word lines and one or more decoders;
a first set of digit lines having a first length, the digit lines of the first set coupled to the memory cells of the first plurality and to one or more of the word lines,
wherein the first set of digit lines are each coupled to a first sense amplifier of a first set of sense amplifiers,
wherein the first set of sense amplifiers are only voltage threshold compensating (VTC) sense amplifiers, and
wherein the VTC sense amplifiers comprise:
a first set of transistors comprising first, second, third, and fourth transistors,
wherein a first digit line of the first set of digit lines is coupled to a gate of the third transistor, and
wherein a second digit line of the first set of digit lines is coupled to a gate of the fourth transistor; and
a second set of transistors comprising fifth, sixth, seventh, and eighth transistors,
wherein the first digit line is coupled to a source of the fifth transistor,
wherein a drain of the fifth transistor is coupled to a node between a drain of the second transistor and a drain of the fourth transistor,
wherein the second digit line is coupled to a source of the sixth transistor,
wherein a drain of the sixth transistor is coupled to a node between a drain of the first transistor and a drain of the third transistor, and
wherein a source of the seventh transistor is coupled to the first digit line, and wherein a source of the eighth transistor is coupled to the second digit line;
a second set of digit lines having a second length that is shorter than the first length, the digit lines of the second set coupled to the memory cells of the second plurality, wherein the second set of digit lines are each coupled to a second sense amplifier of a second set of sense amplifiers, and wherein the second set of sense amplifiers are only non-VTC sense amplifiers;
a plurality of interface connections coupled to the data bus, each connection couplable to a solder pad, wherein the first physical address space is located closer to the interface connections than the second physical address space; and
a controller configured to determine respective performance characteristics associated with the first physical address space and the second physical address space.
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