CPC G11C 11/4091 (2013.01) [G06F 15/7821 (2013.01); G11C 7/1006 (2013.01); G11C 11/4087 (2013.01); G11C 11/4093 (2013.01); G11C 11/4096 (2013.01)] | 20 Claims |
1. A method of operating a memory device including a memory cell array and a processor-in-memory (PIM), the method comprising:
receiving an internal processing mode signal, the internal processing mode signal being transmitted from a memory controller outside of the memory device;
entering an internal processing mode in response to the internal processing mode signal;
uploading internal processing information into the memory cell array, the internal processing information being transmitted from the memory controller during the internal processing mode;
reading the internal processing information from the memory cell array;
performing, by the PIM, an internal processing operation based on the read internal processing information;
determining, by the PIM, whether the read internal processing information includes an internal processing operation command, the internal processing operation command indicating a type of the internal processing operation of the PIM and
generating, by the PIM, the internal processing operation command during the internal processing operation.
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