| CPC G11C 11/4085 (2013.01) [G11C 11/4093 (2013.01); G11C 11/4094 (2013.01); H03M 1/802 (2013.01)] | 20 Claims |
|
1. A computing device, comprising:
a memory array comprising a plurality of memory cells grouped in rows and columns of memory cells, each of the memory cells comprising a memory unit adapted to store data, and a read port having a read-enable input and an output;
a plurality of read-enable lines, each connected to, and adapted to transmit an input signal to, the read-enable inputs of the read ports of a respective row of memory cells;
a plurality of data-output lines, each connected to the outputs of the read ports of a respective column of memory cells; and
an output interface comprising:
a computation module comprising a plurality of capacitors, each being connectable to a respective one of the data-output lines and having a capacitance, at least two of the plurality of capacitors having different capacitance from each other, the output interface being configured to permit the plurality of capacitors to share charge stored on plurality of capacitors,
the plurality of data-output lines forming a multi-digit output, wherein each of the data-output lines corresponds to a respective digit of the multi-digit output and as a respective place value, wherein the capacitances of the at least two of the plurality of capacitors correspond to the place values of the respective data-output lines.
|