US 12,073,863 B2
Memory and electronic device
Yue Pan, Shenzhen (CN); Yanxiang Liu, Shenzhen (CN); and Stephane Badel, Leuven (BE)
Assigned to HUAWEI TECHNOLOGIES CO., LTD., Shenzhen (CN)
Filed by HUAWEI TECHNOLOGIES CO., LTD., Guangdong (CN)
Filed on Jul. 28, 2021, as Appl. No. 17/387,588.
Application 17/387,588 is a continuation of application No. PCT/CN2019/074012, filed on Jan. 30, 2019.
Prior Publication US 2021/0358531 A1, Nov. 18, 2021
Int. Cl. G11C 11/16 (2006.01)
CPC G11C 11/1675 (2013.01) [G11C 11/1655 (2013.01); G11C 11/1657 (2013.01); G11C 11/1673 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A memory further including a storage element, comprising:
a plurality of storage structures arranged in columns;
a first bit line and a second bit line;
a first transistor coupled to the first bit line;
a second transistor coupled to the second bit line, wherein:
the storage element is coupled to the first bit line and the second bit line separately via the first transistor and the second transistor; and
the first transistor and the second transistor are configured to turned on together when a write operation is performed on the storage element; and
wherein in each column of storage structures, first transistors and second transistors are alternately arranged in pairs.