US 12,073,791 B2
Emission control driver including a stage that sets a gate control signal at different times to a first voltage and a second voltage
Haijung In, Yongin-si (KR); Chulkyu Kang, Yongin-si (KR); Soongi Kwon, Yongin-si (KR); Minjeong Kim, Yongin-si (KR); and Kimyeong Eom, Yongin-si (KR)
Assigned to Samsung Display Co., Ltd., Yongin-Si (KR)
Filed by Samsung Display Co., Ltd., Yongin-Si (KR)
Filed on May 19, 2022, as Appl. No. 17/748,926.
Claims priority of application No. 10-2021-0149948 (KR), filed on Nov. 3, 2021.
Prior Publication US 2023/0140806 A1, May 4, 2023
Int. Cl. G09G 3/3258 (2016.01)
CPC G09G 3/3258 (2013.01) [G09G 2300/0426 (2013.01); G09G 2310/08 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A driver that provides a gate control signal to a pixel of a display apparatus, the driver comprising a stage, the stage comprising:
an input terminal configured to receive a start signal;
a first power input terminal configured to receive a first voltage of an on-voltage level;
a second power input terminal configured to receive a second voltage of an off-voltage level;
a first clock terminal configured to receive a first clock signal;
a second clock terminal configured to receive a second clock signal;
a first controller configured to control a voltage level of a first node based on the start signal and the first clock signal;
a second controller configured to control each of voltage levels of a second node and a third node;
a first output terminal; and
a first output unit configured to output the gate control signal to the first output terminal, the first output unit comprising a first pull-up transistor and a second pull-up transistor, a gate terminal of the first pull-up transistor being connected to the second node, a gate terminal of the second pull-up transistor being connected to the third node,
wherein the first output unit is configured to output the gate control signal having the first voltage to the first output terminal through the first pull-up transistor when the second node is in an on-voltage level state, and the first output unit is configured to output the gate control signal having the first voltage to the first output terminal through the second pull-up transistor when the third node is in the on-voltage level state.