US 12,073,769 B2
Display pixels having integrated memory
Douglas Huard, Portland, OR (US); Vishal Sinha, Portland, OR (US); Paul Diefenbaugh, Portland, AZ (US); Khaled Ahmed, San Jose, CA (US); Kristoffer Fleming, Chandler, AZ (US); and Kunjal Parikh, Fremont, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 22, 2020, as Appl. No. 17/131,415.
Prior Publication US 2021/0150979 A1, May 20, 2021
Int. Cl. G09G 3/32 (2016.01)
CPC G09G 3/32 (2013.01) [G09G 2300/0857 (2013.01); G09G 2310/08 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A pixel circuitry array comprising:
first pixel circuitry including:
a first light emitter on a first semiconductor substrate;
memory co-located with the light emitter on the first semiconductor substrate; and
a first comparator in circuit with the memory, the first comparator to control a flow of electrical current to the first light emitter based on pixel data from the memory and timing information; and
second pixel circuitry including:
a second light emitter on a second semiconductor substrate separate from the first semiconductor substrate; and
a second comparator on the second semiconductor substrate to control a flow of electrical current to the second light emitter based on the pixel data from the memory on the first semiconductor substrate and the timing information.