| CPC G06N 3/04 (2013.01) [G06F 17/153 (2013.01); G06F 17/16 (2013.01); G06N 3/08 (2013.01); G06T 9/002 (2013.01); G06F 9/3001 (2013.01)] | 19 Claims |
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1. A processor, comprising:
a first register for storing a first weight value;
a second register for storing a second weight value;
a buffer for storing a first activation value and a second activation value;
a first multiplier;
a second multiplier; and
a first adder;
wherein the buffer includes:
a first queue connected to the first multiplier, the first queue having a first register and a second register; and
a second queue connected to the second multiplier,
wherein, in a first state, the first multiplier is configured to multiply the first weight value by the first activation value from the first register of the first queue, and in a second state, the first multiplier is configured to multiply the first weight value by the second activation value from the second register of the first queue, and
wherein the first adder is connected to an output of the first multiplier based on the first register of the first queue containing zero value.
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