CPC G06F 9/542 (2013.01) [G06F 9/4881 (2013.01); G06F 9/546 (2013.01); G06F 2209/548 (2013.01)] | 16 Claims |
1. An apparatus, comprising:
at least one processor; and
at least one memory storing instructions which, when executed by the at least one processor, cause the apparatus to:
maintain, by a message bus for a set of nodes, a set of event queues for an event type;
determine, by the message bus based on monitoring of the event queues, event queue status information including respective sets of queue status information associated with the respective event queues;
control, by the message bus based on the event queue status information, storage of a set of events of the event type in the set of event queues;
modify, by the message bus based on an indication of a scaling of the set of nodes for the event type based on the event queue status information, a mapping of respective subsets of the event queues to respective ones of the nodes; and
send, by the message bus toward the set of nodes based on the mapping, the set of events of the event type.
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