US 12,073,255 B2
Technologies for providing latency-aware consensus management in a disaggregated architecture
Mrittika Ganguli, Tempe, AZ (US); Murugasamy K. Nachimuthu, Beaverton, OR (US); Muralidharan Sundararajan, Portland, OR (US); Susanne M. Balle, Hudson, NH (US); and Mohan J. Kumar, Aloha, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jul. 2, 2019, as Appl. No. 16/460,371.
Prior Publication US 2019/0324811 A1, Oct. 24, 2019
Int. Cl. G06F 9/50 (2006.01); H04L 67/1008 (2022.01); H04L 67/1031 (2022.01)
CPC G06F 9/505 (2013.01) [H04L 67/1008 (2013.01); H04L 67/1031 (2013.01)] 23 Claims
OG exemplary drawing
 
1. An apparatus comprising:
circuitry to:
determine latencies associated with active performance of operations at subsystems of a disaggregated system, the subsystems on one or more devices remotely located to the circuitry, the subsystems to include at least one accelerator device, compute device, and memory device; and
determine, as a function of the determined latencies, an amount of time in which a configuration change to at least one of the subsystems for which the subsystems of the disaggregated system are to reach a consistent state.