first network interface element to receive an absolute network time-of-day signal from a wireless data communication network;

a memory to store a sequence of one or more instructions from an instruction set of a first processing circuit, the sequence of one or more instructions comprising a stored first instruction that includes an embedded relative predetermined execution time, in time-of-day, relative to the absolute first network time-of-day signal; and

the first processing circuit is configured to use the first instruction and the embedded relative first predetermined execution time, in time-of-day, relative to the absolute first network time-of-day signal, to synchronize execution of a stored second instruction with the absolute network time-of-day signal, wherein the first processing circuit comprises a first synchronization element to:

synchronize a first internal clock with the absolute network time-of-day signal; and

execute the sequence of one or more instructions in synchrony with the first internal clock,

wherein the first processing circuit is configured to wirelessly couple to a second system by the wireless data communication network, wherein the second system includes:

a second network interface element to receive the absolute network time-of-day signal from the wireless data communication network; and

a second processing circuit to execute a third instruction in synchrony with execution of the second instruction by the first processing circuit by using the absolute network time-of-day signal, wherein the second processing circuit includes a second synchronization element to:

synchronize a second internal clock with the absolute network time-of-day signal; and

execute a second sequence of one or more instructions in synchrony with the second internal clock.