US 12,073,227 B2
Energy-efficient core voltage selection apparatus and method
Noor Mubeen, Bangalore (IN); Ashraf H. Wadaa, Beaverton, OR (US); Andrey Gabdulin, Ramat-Gan (IL); Russell Fenger, Beaverton, OR (US); Deepak Samuel Kirubakaran, Hillsboro, OR (US); Marc Torrant, Folsom, CA (US); Ryan Thompson, Beaverton, OR (US); Georgina Saborio Dobles, Pavas (CR); and Lingjing Zeng, Shanghai (CN)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 22, 2020, as Appl. No. 17/131,547.
Claims priority of provisional application 63/069,622, filed on Aug. 24, 2020.
Prior Publication US 2022/0058029 A1, Feb. 24, 2022
Int. Cl. G06F 9/4401 (2018.01); G06F 9/38 (2018.01); G06F 9/50 (2006.01)
CPC G06F 9/4405 (2013.01) [G06F 9/3877 (2013.01); G06F 9/4403 (2013.01); G06F 9/5094 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A non-transitory machine-readable storage media having machine-readable instructions that when executed cause one or more processors to perform a method comprising:
reading a minimum operation voltage (Vmin) per processor core in a multi-core system;
ranking, from a highest ranking to a lowest ranking, each processor core of the multi-core system according to the Vmin per processor core; and
modifying an existing bootstrap processor by assigning a new bootstrap processor to a processor core having the highest ranking.