CPC G06F 9/3838 (2013.01) [G06F 9/30043 (2013.01)] | 29 Claims |
1. A microprocessor, comprising:
a load queue;
a store queue; and
a load/store unit configured to:
during execution of a store instruction:
record store information to an entry of the store queue allocated to the store instruction, wherein the store information comprises store address and store size information about store data to be stored by the store instruction;
during execution of a load instruction that is younger in program order than the store instruction:
perform forwarding behavior with respect to forwarding or not forwarding the store data from the store instruction to the load instruction;
record load information to an entry of the load queue allocated to the load instruction, wherein the load information comprises load address and load size information about load data to be loaded by the load instruction; and
record the forwarding behavior in the load queue entry; and
during commit of the store instruction:
use the recorded store information and the recorded load information and the recorded forwarding behavior to check correctness of the forwarding behavior.
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