US 12,073,217 B2
Memory system and data processing system including the same
Dong Uk Lee, Seoul (KR); Seung Gyu Jeong, Gwangmyeong (KR); and Dong Ha Jung, Yongin (KR)
Assigned to SK hynix Inc., Icheon (KR)
Filed by SK hynix Inc., Icheon (KR)
Filed on Dec. 2, 2022, as Appl. No. 18/061,370.
Application 18/061,370 is a division of application No. 16/860,850, filed on Apr. 28, 2020, granted, now 11,544,063.
Application 16/860,850 is a continuation in part of application No. 16/383,371, filed on Apr. 12, 2019, granted, now 10,963,395, issued on Mar. 30, 2021.
Application 16/860,850 is a continuation in part of application No. 16/352,676, filed on Mar. 13, 2019, granted, now 10,762,012, issued on Dec. 8, 2020.
Application 16/860,850 is a continuation in part of application No. 16/288,015, filed on Feb. 27, 2019, granted, now 10,860,498, issued on Sep. 1, 2020.
Claims priority of application No. 10-2018-0144288 (KR), filed on Nov. 21, 2018; application No. 10-2018-0152527 (KR), filed on Nov. 30, 2018; and application No. 10-2018-0152528 (KR), filed on Nov. 30, 2018.
Prior Publication US 2023/0094634 A1, Mar. 30, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/30 (2018.01); G06F 9/48 (2006.01); G06F 12/02 (2006.01); G06F 12/0882 (2016.01); G06F 13/16 (2006.01); G11C 5/02 (2006.01); G11C 11/4093 (2006.01); G11C 29/42 (2006.01); G11C 29/44 (2006.01)
CPC G06F 9/30047 (2013.01) [G06F 9/4818 (2013.01); G06F 12/0246 (2013.01); G06F 12/0882 (2013.01); G06F 13/1663 (2013.01); G11C 5/025 (2013.01); G11C 11/4093 (2013.01); G11C 29/42 (2013.01); G11C 29/44 (2013.01)] 26 Claims
OG exemplary drawing
 
1. A packaged memory device comprising:
a first chip configured to perform a first operation;
a stacked memory device configured to include a stacked structure of a plurality of memories, the stacked memory device being configured to be accessed by the first chip through a shared bus, the shared bus including a first bus electrically coupling a first interface circuit to a second interface circuit and including a second bus electrically coupling the first bus to the plurality of memories; and
a buffer layer configured to electrically couple the shared bus to the first chip.