US 12,073,200 B2
Compiler device, instruction generation method, program, compiling method, and compiler program
Shogo Murai, Tokyo (JP); Shinichiro Hamaji, Tokyo (JP); and Taiju Tsuiki, Tokyo (JP)
Assigned to Preferred Networks, Inc., Tokyo (JP)
Filed by Preferred Networks, Inc., Tokyo (JP)
Filed on Oct. 24, 2022, as Appl. No. 18/048,937.
Claims priority of application No. 2021-173842 (JP), filed on Oct. 25, 2021.
Prior Publication US 2023/0131430 A1, Apr. 27, 2023
Int. Cl. G06F 8/41 (2018.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01)
CPC G06F 8/445 (2013.01) [G06F 9/30076 (2013.01); G06F 9/3887 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A compiler device for generating an instruction sequence to be executed by an arithmetic processing device, the compiler device comprising at least one memory and at least one processor,
wherein the at least one processor is configured to:
receive a first instruction sequence for executing a first process and a second instruction sequence for executing a second process to be executed after the first process;
generate one or more third instructions, each third instruction being generated by merging a first instruction included in the first instruction sequence and a second instruction included in the second instruction sequence, the first instruction and the second instruction being executable in parallel; and
generate a third instruction sequence by concatenating the one or more third instructions, instructions included in the first instruction sequence that are not merged into the one or more third instructions, and instructions included in the second instruction sequence that are not merged into the one or more third instructions.