| CPC G06F 7/4876 (2013.01) [G06F 5/012 (2013.01); G06F 7/5443 (2013.01); G06F 9/3001 (2013.01)] | 23 Claims |
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1. A processor-implemented method using an n-bit floating point multi-format multiplier circuitry of a processor, the method comprising:
generating by the n-bit floating point multi-format multiplier circuitry, in real-time with respect to respective operatings of the processor, corresponding output values based on respective plural input values, the corresponding output values including second output values in an n-bit floating point format having a second dynamic range and first output values that are not representable in the n-bit floating point format and are representable in an n-bit extension floating point format having a first dynamic range, where absolute values of non-zero values in the first dynamic range are zeroed out in the n-bit floating point format,
wherein the generating of the corresponding output values includes:
using an m-bit digital value multiplier of the n-bit floating point multi-format multiplier circuitry generating, in real-time with respect to a corresponding first operating of the processor at a first point in time, a first k-bit binary value based on a first significand of a first input floating point value and a second significand of a second input floating point value, wherein n, m, and k are natural numbers, m is less than n, and n is less than k;
using a wide dynamic range normalizer circuitry of the n-bit floating point multi-format multiplier circuitry generating, in real-time with respect to the corresponding first operating of the processor, a first output value based on the first k-bit binary value and dependent on respective exponents of the first and second input floating point values, where the generating of the first output value further comprises setting an extension flag to indicate that the first output value is in the n-bit extension floating point format, and outputting the first output value and the extension flag that indicates that the first output value is in the n-bit extension floating point format; and
using the wide dynamic range normalizer circuitry generating, in real-time with respect to a corresponding second operating of the processor at a different second point in time, a second output value in the n-bit floating point format dependent on respective exponents of third and fourth input floating point values and based on a second k-bit binary value output of the m-bit digital value multiplier with respect to the third and fourth input floating point values, where the generating of the second output value further comprises outputting the second output value,
wherein the first, second, third, and fourth input floating point values are values among the respective plural input values, the first output value is a value determined to be among the first output values, and the second output value is a value determined to be among the second output values, and
wherein the n-bit floating point multi-format multiplier circuitry generates the corresponding output values according to a third dynamic range that includes the first and second dynamic ranges.
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