US 12,073,190 B2
Neural network device for neural network operation, operating method of the neural network device, and application processor including the same
Hyunpil Kim, Seoul (KR); Hyunwoo Sim, Seoul (KR); Seongwoo Ahn, Yongin-si (KR); Hasong Kim, Hwaseong-si (KR); and Doyoung Lee, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO, LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Mar. 25, 2021, as Appl. No. 17/212,474.
Claims priority of application No. 10-2020-0042409 (KR), filed on Apr. 7, 2020; and application No. 10-2021-0014396 (KR), filed on Feb. 1, 2021.
Prior Publication US 2021/0311703 A1, Oct. 7, 2021
Int. Cl. G06F 7/487 (2006.01); G06F 7/544 (2006.01)
CPC G06F 7/4876 (2013.01) [G06F 7/5443 (2013.01); G06F 2207/3824 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A neural network device, the neural network device comprising:
a calculation circuit that includes a first multiplier, a second multiplier, an align shifter, an adder, and a first post adder,
wherein the adder shares the first multiplier and the second multiplier,
wherein the calculation circuit performs a first dot product operation on a plurality of floating point data pairs or a second dot product operation on a plurality of integer data pairs,
wherein in the first dot product operation, the calculation circuit
obtains a plurality of fraction multiplication results from the plurality of floating point data pairs, respectively, using the first multiplier,
performs an align shift of the plurality of fraction multiplication results based on a maximum value identified from a plurality of exponent addition results that respectively correspond to the plurality of floating point data pairs using the align shifter,
adds the aligned plurality of fraction multiplication results and generates first cumulative data using the adder,
detects a first leading one by right shifting upper bits of the first cumulative data using the first post adder,
detects a second leading one by right shifting lower bits of the first cumulative data that exclude the upper bits of the first cumulative data using the first post adder, and
outputs the first cumulative data using the first post adder, and,
in the second dot product operation, the calculation circuit
obtains a plurality of integer multiplication results from the plurality of integer data pairs, respectively, using the second multiplier,
adds the plurality of integer multiplication results using the adder and
outputs second cumulative data,
wherein the adder comprises:
a first add circuit that adds upper bits, but not lower bits, of the aligned plurality of fraction multiplication results in the first dot product operation; and
a second add circuit that adds lower bits, but not upper bits, of the aligned plurality of fraction multiplication results in the first dot product operation, or adds the plurality of integer multiplication results in the second dot product operation.