CPC G06F 30/392 (2020.01) [G11C 17/16 (2013.01); G11C 17/18 (2013.01); H01L 23/528 (2013.01); H10B 20/20 (2023.02); H01L 23/5252 (2013.01)] | 20 Claims |
1. An anti-fuse array comprising:
first through fourth adjacent columns of anti-fuse bits, wherein
the anti-fuse bits of the first and second anti-fuse bit columns comprise portions of active areas of a first active area column, and
the anti-fuse bits of the third and fourth anti-fuse bit columns comprise portions of active areas of a second active area column;
a first set of conductive segment rows, wherein each row of the first set of conductive segment rows comprises first and second conductive segments positioned between adjacent active areas of the first active area column and a third conductive segment positioned between adjacent active areas of the second active area column; and
a second set of conductive segment rows alternating with the first set of conductive segment rows, wherein each row of the second set of conductive segment rows comprises a fourth conductive segment positioned between adjacent active areas of the first active area column and fifth and sixth conductive segments positioned between adjacent active areas of the second active area column.
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