US 12,073,167 B2
Analog cells utilizing complementary mosfet pairs
Chung-Ting Lu, Kaohsiung (TW); Chih-Chiang Chang, Taipei (TW); Chung-Peng Hsieh, New Taipei (TW); Chung-Chieh Yang, Zhubei (TW); Yung-Chow Peng, Hsinchu (TW); Yung-Shun Chen, Hsinchu (TW); Tai-Yi Chen, Hsinchu (TW); and Nai Chen Cheng, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Feb. 3, 2023, as Appl. No. 18/163,916.
Application 18/163,916 is a continuation of application No. 17/135,565, filed on Dec. 28, 2020, granted, now 11,574,104.
Application 17/135,565 is a continuation of application No. 16/527,295, filed on Jul. 31, 2019, granted, now 10,878,160, issued on Dec. 29, 2020.
Prior Publication US 2023/0186008 A1, Jun. 15, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 30/392 (2020.01); G06F 30/36 (2020.01); G06F 30/367 (2020.01); G06F 30/394 (2020.01)
CPC G06F 30/392 (2020.01) [G06F 30/36 (2020.01); G06F 30/367 (2020.01); G06F 30/394 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A system for developing an electronic architectural design layout for circuitry of an electronic device, the system comprising:
a memory that stores a plurality of categories of circuits, each category of circuits from among the plurality of categories of circuits being associated with a corresponding common arrangement from among a plurality of common arrangements; and
a processor configured to execute a placing and routing application, the placing and routing application, when executed by the processor, configuring the processor to:
assign a circuit from among a plurality of circuits of the circuitry to a category of circuits from among the plurality of categories of circuits that is associated with a similar corresponding common arrangement as the circuit,
designate a placement site from among the electronic architectural design layout as being assigned to the category of circuits, and
place a standard cell from among a plurality of standard cells that is associated with the category of circuits into the placement site.