US 12,073,165 B2
Standard cell design
Shu-Wei Chung, Taichung (TW); Tung-Heng Hsieh, Hsinchu County (TW); Chung-Hui Chen, HsinChu (TW); and Chung-Yi Lin, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Sep. 16, 2021, as Appl. No. 17/476,615.
Claims priority of provisional application 63/211,738, filed on Jun. 17, 2021.
Prior Publication US 2022/0405457 A1, Dec. 22, 2022
Int. Cl. G06F 30/30 (2020.01); G06F 30/323 (2020.01); G06F 30/392 (2020.01); G06F 30/398 (2020.01); G06F 111/20 (2020.01)
CPC G06F 30/392 (2020.01) [G06F 30/323 (2020.01); G06F 30/398 (2020.01); G06F 2111/20 (2020.01)] 20 Claims
OG exemplary drawing
 
1. An analog standard cell fabricated on a substrate, comprising:
a first active region and a second active region extending side-by-side along a first direction; and
a plurality of conductive lines in a first metal layer over the first active region and the second active region, the plurality of conductive lines comprising:
a first conductive line and a second conductive line extending along the first direction and disposed directly over the first active region,
a third conductive line and a fourth conductive line extending along the first direction and disposed directly over the second active region,
a middle conductive line disposed between the second conductive line and the third conductive line,
a first power line spaced apart from the middle conductive line by the first conductive line and the second conductive line, and
a second power line spaced apart from the middle conductive line by the third conductive line and the fourth conductive line.