	US 12,073,156 B2
	Propagating physical design information through logical design hierarchy of an electronic circuit
Amit Jalota, Fremont, CA (US); Andrew Saunders, Reading (GB); Aruna Kanagaraj, Karnataka (IN); Douglas Chang, San Jose, CA (US); Eshwari Rajendran, Karnataka (IN); Prashant Gupta, Karnataka (IN); Rajeev Murgai, Bangalore (IN); Soumitra Majumder, West Bengal (IN); Vasiliki Chatzi, Santa Clara, CA (US); and Balkrishna Ramchandra Rashingkar, Sunnyvale, CA (US)
Assigned to Synopsys, Inc., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Mountain View, CA (US)
Filed on Mar. 15, 2022, as Appl. No. 17/695,712.
Claims priority of application No. 202141011081 (IN), filed on Mar. 16, 2021.
Prior Publication US 2022/0300687 A1, Sep. 22, 2022
Int. Cl. G06F 30/30 (2020.01); G06F 30/31 (2020.01); G06F 30/32 (2020.01); G06F 30/392 (2020.01); G06F 30/398 (2020.01)

CPC G06F 30/31 (2020.01) [G06F 30/32 (2020.01); G06F 30/392 (2020.01); G06F 30/398 (2020.01)]

20 Claims

1. A computer-implemented method for determining physical design information along a logic hierarchy of a circuit design, the method comprising:

accessing a physical design metric associated with different parts of a physical design of a circuit;

accessing a logic design of the circuit comprising a hierarchy of logic blocks;

determining, by a processor, the physical design metric associated with one or more logic blocks of the hierarchy of the logic design based on a relation between the physical design and the logic design, the determining comprising, propagating aggregate data up the hierarchy by aggregating metrics at circuit blocks at physical design level to obtain aggregate metrics for higher level circuit blocks corresponding to the one or more logic blocks of the hierarchy of the logic design;

configuring a user interface to display the hierarchy of the logic design of the circuit along with the physical design metric associated with the one or more logic blocks of the hierarchy; and

sending the configured user interface for display.