US 12,073,121 B2
Command timer interrupt
Chandrakanth Rapalli, Hyderabad (IN); Yoav Weinberg, Toronto (CA); and Tal Sharifie, Lehavim (IL)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Oct. 20, 2022, as Appl. No. 18/048,292.
Prior Publication US 2024/0134567 A1, Apr. 25, 2024
Prior Publication US 2024/0231685 A9, Jul. 11, 2024
Int. Cl. G06F 12/00 (2006.01); G06F 3/06 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0631 (2013.01); G06F 3/0673 (2013.01)] 25 Claims
OG exemplary drawing
 
1. An apparatus, comprising: a controller associated with a memory device, wherein the controller is configured to cause the apparatus to:
receive, at a protocol controller of a memory system, a command associated with a range of logical addresses of the memory system;
transmit an indication of the command from a queue of the protocol controller of the memory system to a command controller of the memory system;
initiate a timer associated with the queue based at least in part on transmitting the command; and
issue an interrupt command to the command controller of the memory system based at least in part on determining that the timer has expired.