| CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0622 (2013.01); G06F 3/0635 (2013.01); G06F 3/0679 (2013.01)] | 21 Claims |
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1. A memory controller, comprising:
a command queue loader circuit for receiving incoming memory access commands and loading entries of a plurality of entry stacks;
a command queue including said plurality of entry stacks, each entry stack including: a plurality of entries each for holding memory access commands, one or more parameter indicators each a variable and holding a respective characteristic common to the plurality of entries, and a head indicator designating a current entry for arbitration, wherein the command queue loader circuit is operative to load a selected new incoming command into a selected empty entry stack and updates the one or more parameter indicators of the selected empty entry stack to match the at least one common characteristic of the selected new incoming command;
a first arbiter for selecting memory access commands from the command queue for transmission to a memory coupled to a memory channel, the first arbiter including a single command input for each entry stack; and
a credit control circuit for handling flow control credits for a data fabric from which memory access commands are received as memory access requests and decoded before being loaded into the command queue, the credit control circuit operable to retain a credit responsive to a respective memory access command being loaded into a previously empty entry stack, and return a credit to the data fabric responsive to the respective memory access command being loaded into an entry stack already holding at least one memory access command.
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