US 12,073,107 B2
Memory sub-system for monitoring mixed mode blocks
Jianmin Huang, San Carlos, CA (US); Xiangang Luo, Fremont, CA (US); Chun Sum Yeung, San Jose, CA (US); and Kulachet Tanpairoj, San Mateo, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jul. 19, 2021, as Appl. No. 17/378,970.
Prior Publication US 2023/0015066 A1, Jan. 19, 2023
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0652 (2013.01) [G06F 3/0616 (2013.01); G06F 3/0653 (2013.01); G06F 3/0688 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a block program erase count (PEC) component to perform operations comprising:
for each free block of a plurality of free blocks, maintaining multiple PECs corresponding to different respective types of blocks;
for each one of the different respective types of blocks, determining a corresponding total PEC for the plurality of free blocks, wherein the corresponding total PEC is a sum of the PECs corresponding to the one of the different respective types of blocks for all of the plurality of free blocks;
determining a particular type of block to which host data is to be written;
for each free block of the plurality of free blocks, determining a ratio between a PEC corresponding to the respective free block for the determined particular type of block to which the host data is to be written and the corresponding total PEC for the plurality of free blocks to generate a corresponding ratio for the respective free block;
determining the free block of the plurality free blocks having a lowest corresponding ratio; and
writing the host data to the free block determined to have the lowest corresponding ratio.