CPC G06F 3/0613 (2013.01) [G06F 3/0655 (2013.01); G06F 3/0679 (2013.01)] | 26 Claims |
1. A flash memory controller to be used in a storage device and coupled to a flash memory device of the storage device through a specific communication interface, comprising:
an input/output (I/O) circuit, coupled to the flash memory device through the specific communication interface, for sending commands and data between the flash memory device and a processor; and
the processor, coupled to the I/O circuit, for controlling the I/O circuit using a set-feature signal, which carries a set-feature command, a macro execution feature address, and corresponding macro execution parameter information, as a macro execution signal and transmitting the macro execution signal to the flash memory device to make the flash memory device execute multiple set-feature operations of multiple set-feature signals respectively having unique information defined by the corresponding macro execution parameter information carried in the macro execution signal, wherein the corresponding macro execution parameter information is used to indicate the multiple set-feature operations of the multiple set-feature signals to be triggered and executed by the set-feature signal;
wherein the processor controls the I/O circuit sequentially transmitting a prefix signal and a first set-feature signal, which follows the prefix signal, to generate and transmit a command sequence to the flash memory device; the prefix signal sequentially comprises a first macro command and an index value of the first set-feature signal which is followed by the set-feature command in the first set-feature signal; the first macro command is used to indicate instantly executing or not instantly executing a set-feature operation of the first set-feature signal when the first set-feature signal is received by the flash memory device.
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