US 12,073,082 B2
High capacity memory circuit with low effective latency
Youn Cheul Kim, Saratoga, CA (US); Richard S. Chernicoff, Mercer Island, WA (US); Khandker Nazrul Quader, Santa Clara, CA (US); Robert D. Norman, Pendleton, OR (US); Tianhong Yan, Saratoga, CA (US); Sayeef Salahuddin, Walnut Creek, CA (US); and Eli Harari, Saratoga, CA (US)
Assigned to SUNRISE MEMORY CORPORATION, San Jose, CA (US)
Filed by SUNRISE MEMORY CORPORATION, San Jose, CA (US)
Filed on Apr. 24, 2023, as Appl. No. 18/306,073.
Application 18/306,073 is a continuation of application No. 17/169,387, filed on Feb. 5, 2021, granted, now 11,675,500.
Claims priority of provisional application 62/971,720, filed on Feb. 7, 2020.
Prior Publication US 2023/0259283 A1, Aug. 17, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/00 (2006.01); G06F 3/06 (2006.01); H01L 23/00 (2006.01); H01L 25/18 (2023.01)
CPC G06F 3/0611 (2013.01) [G06F 3/0631 (2013.01); H01L 24/20 (2013.01); H01L 25/18 (2013.01); H01L 2224/211 (2013.01); H01L 2224/214 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1435 (2013.01)] 60 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a first semiconductor die having memory circuits of a first type formed thereon wherein memory circuits of the first type have at least one layer of memory cells formed above a substrate layer in the first semiconductor die; and
a second semiconductor die with memory circuits of a second type formed thereon, wherein memory circuits of the second type have a shorter write latency than that of the memory circuits of the first type, and wherein the memory circuits of the first type and memory circuits of the second type are interconnected by wafer-level or chip-level bonding formed between the first and second semiconductor dies.