US 12,073,006 B2
Hardware countermeasures in a fault tolerant security architecture
Amritpal Singh Mundra, Allen, TX (US)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Aug. 2, 2021, as Appl. No. 17/391,132.
Application 17/391,132 is a continuation of application No. 16/048,711, filed on Jul. 30, 2018, granted, now 11,080,432.
Prior Publication US 2021/0357536 A1, Nov. 18, 2021
Int. Cl. G06F 21/75 (2013.01); G06F 21/85 (2013.01); H03K 17/22 (2006.01); H04L 9/00 (2022.01)
CPC G06F 21/755 (2017.08) [G06F 21/85 (2013.01); H03K 17/223 (2013.01); H04L 9/004 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A system comprising:
a processor;
a bus subsystem coupled to the processor that includes a set of firewalls each configured to couple the processor to a respective device of a set of devices; and
a security manager coupled to the bus subsystem that includes a set of security control registers, wherein:
the set of security control registers includes a first subset configured to store a first value; and
the security manager is configured to determine whether to cause a first firewall to operate in a bypass mode based on whether bit values of the first value satisfy a specific criterion with respect to each other, wherein the specific criterion is that the bit values of the first value are an equal Hamming distance away from each other.