US 12,072,952 B2
Data compressor for approximation of matrices for matrix multiply operations
Swapnil P. Sakharshete, San Diego, CA (US); Pramod Vasant Argade, San Diego, CA (US); Maxim V. Kazakov, San Diego, CA (US); and Alexander M. Potapov, San Diego, CA (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Mar. 26, 2021, as Appl. No. 17/214,779.
Prior Publication US 2022/0309125 A1, Sep. 29, 2022
Int. Cl. G06F 17/16 (2006.01); G06F 7/523 (2006.01); G06F 7/544 (2006.01); H03K 19/173 (2006.01)
CPC G06F 17/16 (2013.01) [G06F 7/523 (2013.01); G06F 7/5443 (2013.01); H03K 19/1737 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A processing device comprising:
memory configured to store data; and
a processor, communicatively coupled to the memory, comprising:
a plurality of multiplier accumulators (MACs) configured to perform matrix multiplication of elements of a first matrix and elements of a second matrix;
logic circuitry configured to sum values of bits of corresponding significance of product exponent values of the elements of the first matrix and the second matrix and generate keep bit values for product exponent values to be kept for matrix multiplication; and
a plurality of multiplexor arrays each configured to:
receive bits of the elements of the first matrix and the second matrix and the keep bit values; and
provide data for selecting which elements of the first matrix and the second matrix are provided to the MACs for matrix multiplication,
wherein the processor selects which elements are provided to the MACs based on a comparison, by the logic circuitry, of the summed values of the bits of corresponding significance to a target number of product exponent values.