US 12,072,829 B2
System and method for flexibly crossing packets of different protocols
Nima Nikuie, San Francisco, CA (US); and Lijish Remani Bal, Port Coquitlam (CA)
Assigned to Microchip Technology Incorporated, Chandler, AZ (US)
Filed by Microchip Technology Incorporated, Chandler, AZ (US)
Filed on Oct. 26, 2022, as Appl. No. 17/973,894.
Claims priority of provisional application 63/273,199, filed on Oct. 29, 2021.
Prior Publication US 2023/0134215 A1, May 4, 2023
Int. Cl. G06F 13/42 (2006.01); G06F 9/448 (2018.01)
CPC G06F 13/4226 (2013.01) [G06F 9/4498 (2018.02); G06F 2213/0026 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus for coupling a first and a second data bus, comprising:
a first bus interface having a first number of egress lanes and a first number of ingress lanes;
a second bus interface having a second number of egress lanes and a second number of ingress lanes;
wherein the first number of egress lanes is less than the second number of ingress lanes;
a plurality of egress selectors, each egress selector having an output coupled to an input of one of a plurality of egress memories and each egress selector having a plurality of inputs coupled to the first bus interfaces egress lanes wherein each egress selector may select any one of the first bus egress lanes to output to the input of the corresponding egress memory;
each egress memory having an output coupled to one of the second bus egress lanes, a read enable input coupled to a first finite state machine synchronized to a first clock, and a write enable input coupled to a second finite state machine synchronized to a second clock;
a plurality of ingress selectors, each ingress selector having an output coupled to one of the first bus ingress lanes and each ingress selector having a plurality of inputs coupled to the ingress memories wherein each ingress selector may select the output of any one of the ingress memories to output to the corresponding first bus ingress lane;
each ingress memory having an input coupled to one of the second bus ingress lanes, a write enable input coupled to a third finite state machine synchronized to the second clock, and a read enable input coupled to a fourth finite state machine synchronized to the first clock;
wherein the first finite state machine controls a select input of each of the egress selectors and the fourth finite state machine controls a select input of each of the ingress selectors.