a plurality of central processing units (CPUs) that execute respective software programs independently of each other;

a bus interconnector for connecting the plurality of CPUs; and

at least one access control device that is connected to the bus interconnector and controls each access to a physical resource shared by the plurality of CPUs via the bus interconnector, for each CPU,

wherein the plurality of CPUs comprises at least two CPUs that share physical resources including a memory via a first bus interface and further comprises a resource sharing control device that controls an access to a physical resource exclusively used between the at least two CPUs among the shared physical resources,

wherein the at least two CPUs comprises a first CPU that executes a first software program, and a second CPU that executes a second software program different from the first software program,

wherein the resource sharing control device physically separates a memory region onto which the first software program is loaded among physical resources exclusively used between the at least two CPUs, and blocks an access by the second CPU to the separated memory region,

wherein the plurality of CPUs comprises a third CPU that is connected to a static random access memory (RAM) and a plurality of devices via a second bus interface, and executes a third software program,

wherein the at least one access control device comprises a first access control device that is placed between the second bus interface and the bus interconnector, and controls accesses of other CPUs to the static RAM and the plurality of devices,

wherein the plurality of CPUs comprises a fourth CPU that is connected to a code RAM onto which program codes including a boot code are loaded and a data RAM onto which user data is loaded, via a third bus interface, and executes a fourth software program, and

wherein the at least one access control device further comprises a second access control device that is placed between the third bus interface and the bus interconnector, and controls accesses of other CPUs to the code RAM and the data RAM.