US 12,072,812 B2
Highly integrated scalable, flexible DSP megamodule architecture
Timothy D. Anderson, University Park, TX (US); Joseph Zbiciak, San Jose, CA (US); Duc Quang Bui, Grand Prairie, TX (US); Abhijeet Chachad, Plano, TX (US); Kai Chirca, Dallas, TX (US); Naveen Bhoria, Plano, TX (US); Matthew D. Pierson, Murphy, TX (US); Daniel Wu, Plano, TX (US); and Ramakrishnan Venkatasubramanian, Plano, TX (US)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Apr. 22, 2021, as Appl. No. 17/237,391.
Application 15/429,205 is a division of application No. 14/331,986, filed on Jul. 15, 2014, granted, now 9,606,803, issued on Mar. 28, 2017.
Application 17/237,391 is a continuation of application No. 16/227,238, filed on Dec. 20, 2018, granted, now 11,036,648.
Application 16/227,238 is a continuation of application No. 15/429,205, filed on Feb. 10, 2017, granted, now 10,162,641, issued on Dec. 25, 2018.
Claims priority of provisional application 61/846,148, filed on Jul. 15, 2013.
Prior Publication US 2021/0240634 A1, Aug. 5, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/30 (2018.01); G06F 7/24 (2006.01); G06F 7/487 (2006.01); G06F 7/499 (2006.01); G06F 7/53 (2006.01); G06F 7/57 (2006.01); G06F 9/32 (2018.01); G06F 9/345 (2018.01); G06F 9/38 (2018.01); G06F 9/48 (2006.01); G06F 11/00 (2006.01); G06F 11/10 (2006.01); G06F 12/0862 (2016.01); G06F 12/0875 (2016.01); G06F 12/0897 (2016.01); G06F 12/1009 (2016.01); G06F 12/1045 (2016.01); G06F 17/16 (2006.01); H03H 17/06 (2006.01); G06F 15/78 (2006.01)
CPC G06F 12/1045 (2013.01) [G06F 7/24 (2013.01); G06F 7/487 (2013.01); G06F 7/4876 (2013.01); G06F 7/49915 (2013.01); G06F 7/53 (2013.01); G06F 7/57 (2013.01); G06F 9/3001 (2013.01); G06F 9/30014 (2013.01); G06F 9/30021 (2013.01); G06F 9/30032 (2013.01); G06F 9/30036 (2013.01); G06F 9/30065 (2013.01); G06F 9/30072 (2013.01); G06F 9/30098 (2013.01); G06F 9/30112 (2013.01); G06F 9/30145 (2013.01); G06F 9/30149 (2013.01); G06F 9/3016 (2013.01); G06F 9/32 (2013.01); G06F 9/345 (2013.01); G06F 9/3802 (2013.01); G06F 9/3818 (2013.01); G06F 9/383 (2013.01); G06F 9/3836 (2013.01); G06F 9/3851 (2013.01); G06F 9/3856 (2023.08); G06F 9/3867 (2013.01); G06F 9/3887 (2013.01); G06F 9/48 (2013.01); G06F 11/00 (2013.01); G06F 11/1048 (2013.01); G06F 12/0862 (2013.01); G06F 12/0875 (2013.01); G06F 12/0897 (2013.01); G06F 12/1009 (2013.01); G06F 17/16 (2013.01); H03H 17/0664 (2013.01); G06F 9/30018 (2013.01); G06F 9/325 (2013.01); G06F 9/381 (2013.01); G06F 9/3822 (2013.01); G06F 11/10 (2013.01); G06F 15/7807 (2013.01); G06F 15/781 (2013.01); G06F 2212/452 (2013.01); G06F 2212/60 (2013.01); G06F 2212/602 (2013.01); G06F 2212/68 (2013.01)] 26 Claims
OG exemplary drawing
 
1. An electronic device comprising:
a processor core;
a memory;
a register; and
a data load unit configured to receive a plurality of data elements stored in the memory in response to an instruction that specifies a data size of each element of the plurality of data elements, a number of iterations for each loop of a set of nested loops, and a number of elements between starting points of each loop of the set of nested loops, wherein the data load unit includes:
an address generator to generate addresses corresponding to locations in the memory at which the plurality of data elements are located based on the data size, the number of iterations for each loop of the set of nested loops, and the number of elements between starting points of each loop of the set of nested loops; and
a formatting unit to format the data elements;
wherein the register is configured to store the formatted data elements; and
wherein the processor core is configured to receive the formatted data elements from the register.