US 12,072,811 B2
Namespace level valid translation unit count
Dahai Tian, Shanghai (CN); and Jing Ping Lu, Shanghai (CN)
Assigned to Micron Technology, Inc., Boise, ID (US)
Appl. No. 17/775,090
Filed by Micron Technology, Inc., Boise, ID (US)
PCT Filed Apr. 18, 2022, PCT No. PCT/CN2022/087366
§ 371(c)(1), (2) Date May 6, 2022,
PCT Pub. No. WO2023/201462, PCT Pub. Date Oct. 26, 2023.
Prior Publication US 2023/0333988 A1, Oct. 19, 2023
Int. Cl. G06F 12/1009 (2016.01)
CPC G06F 12/1009 (2013.01) 20 Claims
OG exemplary drawing
 
1. A system comprising:
a set of memory components of a memory sub-system; and
a processing device, operatively coupled to the set of memory components, configured to perform operations comprising:
generating a plurality of namespaces on the memory sub-system, the set of memory components comprising an individual block to store data for the plurality of namespaces, in one or more translational units;
maintaining a table describing a quantity of valid translational unit counts stored on the memory sub-system, the table comprising:
a first count of representing a total number of valid translational units on the individual block; and
a second count representing distribution of the total number of valid translational units across each of the plurality of namespaces for which the data is stored in the individual block;
receiving one or more requests from a host device to add one or more new namespaces to the memory sub-system or remove one or more existing namespaces from the memory sub-system; and
in response to receiving the one or more requests from the host device, processing data stored in the table to add the one or more new namespaces to the individual block or remove a portion of the plurality of namespaces allocated to the individual block.