CPC G06F 12/10 (2013.01) [G06F 12/06 (2013.01); G06F 17/16 (2013.01); G11C 5/144 (2013.01); G11C 5/148 (2013.01); G11C 7/1006 (2013.01); G11C 8/06 (2013.01); G11C 11/419 (2013.01)] | 20 Claims |
1. An apparatus, comprising:
a memory circuit including a plurality of banks, wherein a given one of the plurality of banks includes a plurality of rows of dynamic memory cells; and
a control circuit configured to:
compare a particular refresh address associated with a particular row of the plurality of rows to a plurality of addresses associated with locations in the memory circuit where data that matches a sparse data pattern is stored; and
during a refresh operation, process the particular row, wherein to process the particular row, the control circuit is further configured to:
in response to a determination that the particular refresh address is excluded from the plurality of addresses, refresh the particular row; and
in response to a determination that the particular refresh address is included within the plurality of addresses, omit the particular row from the refresh operation.
|