US 12,072,807 B2
Storage and access of data and tags in a multi-way set associative cache
Thomas Vogelsang, Mountain View, CA (US); Frederick A. Ware, Los Altos Hills, CA (US); Michael Raymond Miller, Raleigh, NC (US); and Collins Williams, Raleigh, NC (US)
Assigned to RAMBUS INC., San Jose, CA (US)
Appl. No. 17/058,492
Filed by RAMBUS INC., San Jose, CA (US)
PCT Filed May 31, 2019, PCT No. PCT/US2019/035045
§ 371(c)(1), (2) Date Nov. 24, 2020,
PCT Pub. No. WO2019/236427, PCT Pub. Date Dec. 12, 2019.
Claims priority of provisional application 62/842,244, filed on May 2, 2019.
Claims priority of provisional application 62/777,639, filed on Dec. 10, 2018.
Claims priority of provisional application 62/680,738, filed on Jun. 5, 2018.
Prior Publication US 2021/0200680 A1, Jul. 1, 2021
Int. Cl. G06F 12/00 (2006.01); G06F 12/0864 (2016.01)
CPC G06F 12/0864 (2013.01) [G06F 2212/6032 (2013.04)] 20 Claims
OG exemplary drawing
 
1. A dynamic random access memory (DRAM), the DRAM comprising:
a plurality of columns, a plurality of data rows and a plurality of tag rows;
a communication interface to receive a first group of address bits from a memory controller; and
a plurality of comparators each to:
compare the first group of address bits and a first group of tag information bits from the plurality of tag rows to generate a cache hit indication and a plurality of set bits; and
combine, based on the cache hit, the plurality of set bits and address bits to generate a second group of address bits to be used to access cache data in the DRAM as a multiway set associative cache, in a plurality of banks of the DRAM.