US 12,072,789 B2
Resumable instruction generation
Michael Brothers, Pflugerville, TX (US); Michael Vaden, Austin, TX (US); Jingliang Wang, Austin, TX (US); Noah Sherrill, Austin, TX (US); and Stephen Edwards, Austin, TX (US)
Assigned to Huawei Technologies Co., Ltd., Shenzhen (CN)
Filed by Huawei Technologies Co., Ltd., Shenzhen (CN)
Filed on Dec. 2, 2022, as Appl. No. 18/074,167.
Application 18/074,167 is a continuation of application No. PCT/US2020/063654, filed on Dec. 7, 2020.
Claims priority of provisional application 63/034,771, filed on Jun. 4, 2020.
Prior Publication US 2023/0101154 A1, Mar. 30, 2023
Int. Cl. G06F 11/27 (2006.01); G06F 9/00 (2018.01); G06F 9/445 (2018.01); G06F 9/455 (2018.01); G06F 11/14 (2006.01); G06F 11/20 (2006.01); G06F 11/36 (2006.01)
CPC G06F 11/3684 (2013.01) [G06F 11/3688 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method performed by an instruction sequence generator (ISG) for generating instruction sequences for testing a processor design model, the method comprising:
receiving an initial test template comprising an initial set of instruction constraints and a save resumable state command;
generating a first set of executable test instructions for testing the processor design model based on the initial test template;
initiating the save resumable state command when the ISG encounters the save resumable state command in the initial test template;
creating a snapshot comprising information on a resume state of the ISG and the first set of executable test instructions in response to initiating the save resumable state command, wherein the snapshot can be used to place the processor design model to a particular internal processor state; and
saving the snapshot.